The pin electronics of a semiconductor test instrument includes a driver for applying a signal to a device under test and a comparator for determining the logic of a signal output from the device under test correspondingly to the signal. The driver outputs a signal synchronizing with an input clock signal. Moreover, the comparator determines synchronously with an input strobe signal.
In the initial state of the semiconductor test instrument, because the time length of a signal route for each input/output pin of the device under test fluctuates, the timing for outputting a signal from the driver or the determination timing of the comparator shifts from an expected timing. Therefore, timing calibration is applied to the device under test before various tests are executed.
FIG. 73 is an illustration showing a conventional configuration of a semiconductor test instrument for performing timing calibration. In FIG. 73, a semiconductor test instrument 90 is connected to a socket board 94 through an exclusive cable 93 provided for a performance board 92. For example, to apply various tests to a device under test having a BGA (Ball Grid Array) type package, the socket board 94 on whose surface many pogo pins are provided. A test board 96 is used to simplify the operation for bringing a probe 99 extended from a reference driver/comparator (DR/CP) section 98 into contact with these pogo pins provided for the surface of the socket board 94 and has a structure in which pads provided for the surface and back are electrically connected each other.
FIG. 74 is an electrical layout diagram of the conventional configuration shown in FIG. 73. The semiconductor test instrument 90 is provided with a plurality of sets of drivers and comparators and each set of a driver and a comparator is connected to a common device socket end through the performance board (PB) 92 and socket board (SB) 94. In FIG. 74, a test board 96 is omitted.
FIGS. 75, 76, and 77 are illustrations showing the outline of conventional timing calibration. As shown in FIG. 75, phases (skews) of clock signals CLK1 to CLKn and strobe signals STB1 to STBn input to n drivers DR1 to DRn and n comparators CP1 to CPn respectively are shifted in the initial state of a semiconductor test instrument.
First, the probe 99 of the reference driver/comparator section 98 is connected to any device socket end through the test board 96 to make the phase of the strobe signal STBL (timing of comparison by comparator CP1) coincide with the rise timing of a reference driver signal (reference DR) (FIG. 76). Then, after the phase of a reference comparator signal (reference CP) is made to coincide with the rise timing of an output signal of the reference driver, the phase of the clock signal CLK1 input to the driver DR1 is adjusted so that the rise timing of a signal output from the driver DR1 coincides with the output timing of the reference comparator signal (timing of comparison by reference comparator) (FIG. 77). The above timing calibration operation is performed every device socket end.
Because the timing calibration method of the above conventional semiconductor test instrument performs timing correction at a device socket end, it is necessary to repeat movement of the probe 99 provided for the reference driver/comparator section 98 and contact of the front end of the probe 99. Therefore, to automate the above operation, a special apparatus is necessary. It is considered to make a robot perform the above operation. However, this type of the robot is generally expensive and it is not easy to handle the robot in order to secure a high optional accuracy in many cases. Therefore, there is a problem that operation contents are complicated. It is possible to manually align the probe 99 without using a robot. However, when a device under test has many pins or there are many devices under test that are tested at the same time, the number of times for repeating movement and contact of the probe 99 greatly increases. Therefore, there is a problem that the working time until timing calibration is completed increases.